kw.\*:("Rejilla transistor")
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Structure of the breakdown spot during progressive breakdown of ultra-thin gate oxidesPALUMBO, F; LOMBARDO, S; PEY, K. L et al.IEEE international reliability physics symposium. 2004, pp 583-584, isbn 0-7803-8315-X, 1Vol, 2 p.Conference Paper
Modeling and characterization of gate oxide reliabilityLEE, J. C; IH-CHIN CHEN; CHENMING HU et al.I.E.E.E. transactions on electron devices. 1988, Vol 35, Num 12, pp 2268-2278, issn 0018-9383Article
A novel gate-suppression technique for ESD protectionMENG MIAO; SHURONG DONG; MINGLIANG LI et al.Microelectronics and reliability. 2012, Vol 52, Num 8, pp 1598-1601, issn 0026-2714, 4 p.Conference Paper
Subnanometer-precision metrology for 100nm gate linewidth controlMONAHAN, K. M; MACNAUGHTON, C; NG, W et al.SPIE proceedings series. 1998, pp 110-123, isbn 0-8194-2777-2Conference Paper
Gate technology for 89 GHz vertical doping engineered Si metal-oxide semiconductor field effect transistorJEON, D. Y; TENNANT, D. M; KIM, Y. O et al.Journal of vacuum science & technology. B. Microelectronics and nanometer structures. Processing, measurement and phenomena. 1992, Vol 10, Num 6, pp 2922-2926, issn 1071-1023Conference Paper
Platinum-platinum oxide gate pH ISFETTSUKADA, K; MIYAHARA, Y; MIYAGI, H et al.Japanese journal of applied physics. 1989, Vol 28, Num 12, pp 2450-2453, issn 0021-4922, 1Article
Evaluation of phase-edge phase-shifting mask for sub-0.18 μm gate patterns in logic devicesCHA, D.-H; KYE, J.-W; SEONG, N.-G et al.SPIE proceedings series. 1998, pp 46-54, isbn 0-8194-2779-9Conference Paper
Advanced gate stack, source/drain and channel engineering for Si-based CMOS : naw materials, processes, and equipment (Quebec PQ, 16-18 May 2005)Gusev, Evgeni P; Iwai, Hiroshi; Öztürk, Mehmet C et al.Proceedings - Electrochemical Society. 2005, issn 0161-6374, isbn 1-56677-463-2, XV, 634 p, isbn 1-56677-463-2Conference Proceedings
Line edge roughness: Characterization, modeling and impact on device behaviorCROON, J. A; STORMS, G; WINKELMEIER, S et al.IEDm : international electron devices meeting. 2002, pp 307-310, isbn 0-7803-7462-2, 4 p.Conference Paper
Effect of n+―polycrystalline silicon gate rapid thermal annealing on the electrical properties of the gate oxideKOREC, J; STEFFEN, A; MCGINTY, G. K et al.Thin solid films. 1988, Vol 162, pp 21-28, issn 0040-6090Article
Symmetrical 45nm PMOS on (110) substrate with excellent S/D extension distribution and mobility enhancementHWANG, J. R; HO, J. H; LIN, H. S et al.Symposium on VLSI Technology. sd, pp 90-91, isbn 0-7803-8289-7, 1Vol, 2 p.Conference Paper
Gate dielectric breakdown : A focus on ESD protectionWEIR, Bonnie E; LEUNG, Che-Choi; SILVERMAN, Paul J et al.IEEE international reliability physics symposium. 2004, pp 399-404, isbn 0-7803-8315-X, 1Vol, 6 p.Conference Paper
0.18 μm optical lithography performances using an alternating DUV phase shift maskTROUILLER, Y; BUFFET, N; MOURIER, T et al.SPIE proceedings series. 1998, pp 25-35, isbn 0-8194-2779-9Conference Paper
A novel method to characterize MOS transistors with mixed gate dielectric technologiesSIERGIEJ, R. R; WHITE, M. H.I.E.E.E. transactions on electron devices. 1992, Vol 39, Num 3, pp 734-737, issn 0018-9383Article
The influence of substrate compensation on inter-electrode leakage and back-gating in GaAs MESFETGEORGE, P; KO, P. K; CHENMING HU et al.Solid-state electronics. 1991, Vol 34, Num 3, pp 233-252, issn 0038-1101, 20 p.Article
Effective work function of NiSi/HfO2 gate stacks measured with X-ray photoelectron spectroscopyLEBEDINSKII, Yu. Yu; ZENKEVICH, A. V.Microelectronics and reliability. 2007, Vol 47, Num 4-5, pp 649-652, issn 0026-2714, 4 p.Conference Paper
Study of stress evolution during full silicidation for gate stacksTORREGIANI, C; KITTI, J. A; CAPPON, S et al.Proceedings - Electrochemical Society. 2005, pp 249-256, issn 0161-6374, isbn 1-56677-463-2, 8 p.Conference Paper
New concept of high-k integration in MOSFET's by a deposition through contact holesHARRISON, S; CORONEL, P; WACQUANT, F et al.Microelectronic engineering. 2004, Vol 72, Num 1-4, pp 321-325, issn 0167-9317, 5 p.Conference Paper
Drastic improvements of gate oxide reliability by argon annealing compared with hydrogen annealingYAMADA, N; YAMADA-KANETA, H.Journal of the Electrochemical Society. 1998, Vol 145, Num 10, pp 3628-3631, issn 0013-4651Article
Does the ESD-failure current obtained by transmission-line pulsing always correlate to human body model tests?STADLER, W; GUGGENMOS, X; EGGER, P et al.Microelectronics and reliability. 1998, Vol 38, Num 11, pp 1773-1780, issn 0026-2714Conference Paper
A simple fabrication process of T-shaped gates using a deep-UV/electron-beam/deep-UV tri-layer resist system and electron-beam lithographyLAI, Y.-L; CHANG, E. Y; CHANG, C.-Y et al.Japanese journal of applied physics. 1996, Vol 35, Num 12B, pp 6440-6446, issn 0021-4922, 1Conference Paper
Hole trapping phenomena in the gate insulator of As-fabricated insulated gate field effect transistorsLIPKIN, L; REISMAN, A; WILLIAMS, C. K et al.Journal of applied physics. 1990, Vol 68, Num 9, pp 4620-4633, issn 0021-8979Article
Lateral diffusion of Na+ ions from the gate edge into the oxide for P+ and N+ polycrystalline silicon gatesTANAKA, H; AIKAWA, I; AJIOKA, T et al.Journal of the Electrochemical Society. 1990, Vol 137, Num 2, pp 644-647, issn 0013-4651Article
Simple method to extract gate voltage dependent source/drain resistance in mosfetsLEE, J. I; LEE, M. B; LEE, Y. J et al.Electronics Letters. 1990, Vol 26, Num 21, pp 1806-1807, issn 0013-5194Article
The effects of various gate oxidation conditions on intrinsic and radiation-induced extrinsic charged defects and neutral electron trapsWALTERS, M; REISMAN, A.Journal of the Electrochemical Society. 1990, Vol 137, Num 11, pp 3596-3601, issn 0013-4651Article